27 search results - page 4 / 6 » IP Validation for FPGAs Using Hardware Object Technology |
FPL
2005
Springer
14 years 4 months ago
2005
Springer
A module generator called Mullet for producing near-optimal parallel multipliers in a technology independent manner is presented. Using this tool, a large number of candidate desi...
FPL
2010
Springer
13 years 8 months ago
2010
Springer
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
ICCAD
2001
IEEE
14 years 7 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
EH
1999
IEEE
14 years 3 months ago
1999
IEEE
We address the fundamental issue of fully automated design (FAD) and construction of inexpensive robots and their controllers. Rather than seek an intelligent general purpose robo...