37 search results - page 5 / 8 » Identification of clock synchronization errors: A behavioral... |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
EWSN
2006
Springer
14 years 7 months ago
2006
Springer
Time synchronization is a crucial component of a large class of sensor network applications, traditionally implemented as a standalone middleware service that provides a virtual gl...
PC
2000
13 years 7 months ago
2000
A common approach to parallelizing simulated annealing to generate several perturbations to the current solution simultaneously, requiring synchronization to guarantee correct eva...
ATAL
2008
Springer
13 years 9 months ago
2008
Springer
Virtual agents designed to establish relationships with more than one user must be able to identify and distinguish among those users with high reliability. We descr...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...