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» Impact of Errors in Operational Spreadsheets
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MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 20 days ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
JVCIR
2007
140views more  JVCIR 2007»
13 years 7 months ago
Robust video streaming over wireless LANs using multiple description transcoding and prioritized retransmission
Video transport over wireless Local Area Networks (LANs) usually suffers from signal fading, noise interference, and network congestion, leading to time-varying packet loss rate ...
Chih-Ming Chen, Chia-Wen Lin, Hsiao-Cheng Wei, Yun...
LCPC
2009
Springer
13 years 12 months ago
Enforcing Textual Alignment of Collectives Using Dynamic Checks
Abstract. Many parallel programs are written in a single-program, multipledata (SPMD) style, in which synchronization is provided using collective operations that all threads execu...
Amir Kamil, Katherine A. Yelick
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 1 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
ISCAS
2002
IEEE
110views Hardware» more  ISCAS 2002»
14 years 10 days ago
Incorporation of input glitches into power macromodeling
Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glit...
Xun Liu, Marios C. Papaefthymiou