305 search results - page 25 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
ICPP
2008
IEEE
14 years 2 months ago
2008
IEEE
The shading processors in graphics hardware are becoming increasingly general-purpose. We test, through simulation and benchmarking, the potential performance impact of replacing ...
CCGRID
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper studies five real-world data intensive workflow applications in the fields of natural language processing, astronomy image analysis, and web data analysis. Data intensiv...
SIGGRAPH
2009
ACM
14 years 2 months ago
2009
ACM
We present a novel parallel continuous collision detection (PCCD) method to utilize the widely available multi-core CPU architecture. Our method works with a wide variety of defor...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
HOTI
2011
IEEE
12 years 7 months ago
2011
IEEE
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...