305 search results - page 29 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploi...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
HPCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...