305 search results - page 33 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
DSN
2009
IEEE
14 years 2 months ago
2009
IEEE
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...
CCGRID
2010
IEEE
13 years 8 months ago
2010
IEEE
In this research, we investigate and address the challenges of asymmetry in High-End Computing (HEC) systems comprising heterogeneous architectures with varying I/O and computation...