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» Impact of Parallel Workloads on NoC Architecture Design
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ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
14 years 13 days ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
HPCA
2001
IEEE
14 years 8 months ago
Dynamic Thermal Management for High-Performance Microprocessors
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
David Brooks, Margaret Martonosi
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
14 years 24 days ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
IPPS
2009
IEEE
14 years 2 months ago
Annotation-based empirical performance tuning using Orio
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
Albert Hartono, Boyana Norris, Ponnuswamy Sadayapp...
IPPS
2008
IEEE
14 years 1 months ago
Scaling alltoall collective on multi-core systems
MPI Alltoall is one of the most communication intense collective operation used in many parallel applications. Recently, the supercomputing arena has witnessed phenomenal growth o...
Rahul Kumar, Amith R. Mamidala, Dhabaleswar K. Pan...