98 search results - page 12 / 20 » Impact of Scaling on the Effectiveness of Dynamic Power Redu... |
ISLPED
2003
ACM
14 years 22 days ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
RTCSA
2008
IEEE
14 years 1 months ago
2008
IEEE
Reliability-aware power management (RAPM) schemes, which consider the negative effects of voltage scaling on system reliability, were recently studied to save energy while preserv...
CSREAESA
2003
13 years 8 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
INTEGRATION
2008
13 years 7 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...