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» Impact of Technology Scaling in the Clock System Power
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OSDI
2000
ACM
14 years 15 days ago
Policies for Dynamic Clock Scheduling
Pocket computers are beginning to emerge that provide sufficient processing capability and memory capacity to run traditional desktop applications and operating systems on them. T...
Dirk Grunwald, Philip Levis, Keith I. Farkas, Char...
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
14 years 4 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
14 years 5 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 4 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ICCAD
2006
IEEE
136views Hardware» more  ICCAD 2006»
14 years 8 months ago
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with
As CMOS technology scales into the nanometer regime, power dissipation and associated thermal concerns in high-performance ICs due to on-chip hot-spots and thermal gradients are b...
Sheng-Chih Lin, Kaustav Banerjee