20 search results - page 1 / 4 » Impact of lithography-friendly circuit layout |
DAC
2009
ACM
14 years 12 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
ASPDAC
2010
ACM
13 years 9 months ago
2010
ACM
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
ISPD
2007
ACM
14 years 13 days ago
2007
ACM
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
DAC
2005
ACM
14 years 25 days ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...