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    IJCAT
    2010
    273views more  IJCAT 2010»
    FPGA implementation of log-polar mapping
    13 years 6 months ago
    FPGA implementation of log-polar mapping
    Download  www1.mmu.edu.my
    Log-polar or spatially-variant image representation is an important component of active vision system in tracking process for many robotic applications due to its data compression ...
    Wai Kit Wong, Chee Wee Choo, Chu Kiong Loo, Joo Pe...
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    VLSISP
    2008
    239views more  VLSISP 2008»
    An Embedded Real-Time Surveillance System: Implementation and Evaluation
    13 years 7 months ago
    An Embedded Real-Time Surveillance System: Implementation and Evaluation
    Download  www.eit.lth.se
    This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
    Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...
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    ERSA
    2008
    92views Hardware» more  ERSA 2008»
    Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
    13 years 9 months ago
    Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
    Download  www.kameyama.ecei.tohoku.ac.jp
    This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks...
    Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
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    FPL
    2003
    Springer
    100views Hardware» more  FPL 2003»
    An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
    14 years 28 days ago
    An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
    Download  www.arl.wustl.edu
    An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
    John W. Lockwood, Christopher E. Neely, Christophe...
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    FPGA
    2007
    ACM
    153views FPGA» more  FPGA 2007»
    GlitchLess: an active glitch minimization technique for FPGAs
    14 years 1 months ago
    GlitchLess: an active glitch minimization technique for FPGAs
    Download  www.ece.ubc.ca
    This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
    Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
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