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ITCC
2005
IEEE
14 years 1 months ago
2005
IEEE
— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2...
RTSS
2005
IEEE
14 years 1 months ago
2005
IEEE
Mapping a set of feedback control components to executable code introduces errors due to a variety of factors such as discretization, computational delays, and scheduling policies...
CHES
2003
Springer
14 years 28 days ago
2003
Springer
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
LCN
2002
IEEE
14 years 18 days ago
2002
IEEE
This paper describes how a portable benchmark suite that measures the ability of an MPI implementation to overlap computation and communication can be used to discover and diagnos...
ISSS
2000
IEEE
14 years 2 days ago
2000
IEEE
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...