3398 search results - page 670 / 680 » Implementations of Grid-Based Distributed Parallel Computing |
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
26
Voted
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
ICS
2010
Tsinghua U.
14 years 5 months ago
2010
Tsinghua U.
We introduce the notion of "non-malleable codes" which relaxes the notion of error-correction and errordetection. Informally, a code is non-malleable if the message cont...
SPAA
2009
ACM
14 years 4 months ago
2009
ACM
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...