248 search results - page 3 / 50 » Implementing Caches in a 3D Technology for High Performance ... |
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
TPDS
2010
13 years 5 months ago
2010
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
MICRO
2003
IEEE
14 years 19 days ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
COMPGEOM
2006
ACM
14 years 1 months ago
2006
ACM
We describe an implementation of a compact parallel algorithm for 3D Delaunay tetrahedralization on a 64-processor shared-memory machine. Our algorithm uses a concurrent version o...