49 search results - page 5 / 10 » Implementing LDPC Decoding on Network-on-Chip |
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
SIPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) algorithm is gaining increased attention in communication standards and literature. The ne...
ICC
2007
IEEE
14 years 2 months ago
2007
IEEE
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical stru...