125 search results - page 23 / 25 » Implementing LNS using filtering units of GPUs |
131
Voted
ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
118
Voted
ERSA
2006
15 years 5 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
263
Voted
ASPLOS
2009
ACM
16 years 4 months ago
2009
ACM
The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-bu...
160
Voted
CF
2009
ACM
15 years 10 months ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
120
Voted
ICRA
2005
IEEE
15 years 9 months ago
2005
IEEE
— We report on progress toward a continuous time full 6 DOF translational body state estimator for a hexapod robot executing a jogging gait (with 4 consecutive phases: tripod sta...