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» Implementing Optimizations at Decode Time
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ICCAD
2003
IEEE
138views Hardware» more  ICCAD 2003»
14 years 5 months ago
Multi-Million Gate FPGA Physical Design Challenges
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Maogang Wang, Abhishek Ranjan, Salil Raje
WECWIS
2009
IEEE
168views ECommerce» more  WECWIS 2009»
14 years 2 months ago
SARI-SQL: Event Query Language for Event Analysis
Complex Event Processing (CEP) systems are capable of processing large amounts of events, utilizing them to monitor, steer and optimize business in real time. The lack of tracking...
Szabolcs Rozsnyai, Josef Schiefer, Heinz Roth
ICCCN
2008
IEEE
14 years 2 months ago
Security Extensions for Space-Link Communication
—In recent times, the importance of information security in civilian space communication systems has increased significantly among space agencies. Those systems often require a ...
Daniel Fischer, Mario Merri, Thomas Engel
ICC
2007
IEEE
14 years 2 months ago
Measurement and Evaluation of ENUM Server Performance
Abstract—ENUM is a DNS-based protocol standard for mapping E.164 telephone numbers to Internet Uniform Resource Identifiers (URIs). It places unique requirements on the existing...
Charles Shen, Henning Schulzrinne
ISCAS
2007
IEEE
122views Hardware» more  ISCAS 2007»
14 years 2 months ago
Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive Control
— A mixed-signal architecture for continuous-time multidimensional model-free optimization is presented. It is based on multi-channel coherent modulation and detection that relia...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...