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» Implementing a STARI chip
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HIPC
2007
Springer
14 years 2 months ago
FFTC: Fastest Fourier Transform for the IBM Cell Broadband Engine
The Fast Fourier Transform (FFT) is of primary importance and a fundamental kernel in many computationally intensive scientific applications. In this paper we investigate its perf...
David A. Bader, Virat Agarwal

Publication
576views
15 years 8 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
DAC
2008
ACM
14 years 9 months ago
Parallelizing CAD: a timely research agenda for EDA
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on paralle...
Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su
DAC
2002
ACM
14 years 9 months ago
Constraint-driven communication synthesis
Constraint-driven Communication Synthesis enables the automatic design of the communication architecture of a complex system from a library of pre-defined Intellectual Property (I...
Alessandro Pinto, Luca P. Carloni, Alberto L. Sang...
DAC
2006
ACM
14 years 9 months ago
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
Reouven Elbaz, Lionel Torres, Gilles Sassatelli, P...