Sciweavers

857 search results - page 137 / 172
» Implementing a STARI chip
Sort
View
CODES
2005
IEEE
14 years 2 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
IPPS
2005
IEEE
14 years 2 months ago
The SDVM - An Approach for Future Adaptive Computer Clusters
The Self Distributing Virtual Machine (SDVM) is a parallel computing machine which consists of a cluster of customary computers. The participating machines may have different comp...
Jan Haase, Frank Eschmann, Klaus Waldschmidt
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
14 years 2 months ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
14 years 2 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
FPL
2005
Springer
226views Hardware» more  FPL 2005»
14 years 2 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...