857 search results - page 15 / 172 » Implementing a STARI chip |
VTC
2010
IEEE
13 years 5 months ago
2010
IEEE
—In this paper we present an architectural analysis of a smart DMA (sDMA) controller for protocol stack acceleration in mobile devices supporting 3GPP’s Long Term Evolution (LT...
ASYNC
2004
IEEE
13 years 11 months ago
2004
IEEE
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new approach in realizing Virtual Channels tailored for Network on Chip implementations. The technique makes use of a flow control mechanism based on adaptiv...
CCECE
2006
IEEE
14 years 1 months ago
2006
IEEE
— The aim of this research is to implement sensorless vector control algorithms on a single, eventually reconfigurable, chip, with a computation timing constraint of, at most, 1...
DSD
2009
IEEE
14 years 2 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...