857 search results - page 167 / 172 » Implementing a STARI chip |
ICALP
1998
Springer
13 years 11 months ago
1998
Springer
Interval Routing Schemes (IRS for short) have been extensively investigated in the past years with special emphasis on shortest paths. Besides their theoretical interest, IRS have...
INFOCOM
1997
IEEE
13 years 11 months ago
1997
IEEE
Current high-speed packet switching systems, ATM in particular, have large port bu ering requirements. The use of highly integrated ASIC technology for implementing high-degree an...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
Profilers play an important role in software/hardware design, optimization, and verification. Various approaches have been proposed to implement profilers. The most widespread app...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...