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» Implementing a STARI chip
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PPL
2008
144views more  PPL 2008»
13 years 7 months ago
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
DATE
2005
IEEE
141views Hardware» more  DATE 2005»
13 years 9 months ago
Multimedia Applications of Multiprocessor Systems-on-Chips
This paper surveys the characteristics of multimedia systems. Multimedia applications today are dominated by compression and decompression, but multimedia devices must also implem...
Wayne Wolf
VLSID
2004
IEEE
168views VLSI» more  VLSID 2004»
14 years 7 months ago
VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design
Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful...
Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Nam...
FCCM
2009
IEEE
169views VLSI» more  FCCM 2009»
14 years 2 months ago
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function
BLASTn is a tool universally used by biologists to identify similarities between nucleotide based biological genome sequences. This report describes an FPGA based hardware impleme...
Siddhartha Datta, Parag Beeraka, Ron Sass
IJCNN
2007
IEEE
14 years 1 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...