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» Implementing a STARI chip
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FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 3 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...
ASYNC
2005
IEEE
79views Hardware» more  ASYNC 2005»
13 years 11 months ago
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of G...
Tobias Bjerregaard, Jens Sparsø
PATMOS
2004
Springer
14 years 3 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 2 months ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...
IWANN
2007
Springer
14 years 3 months ago
Integration of Wind Sensors and Analogue VLSI for an Insect-Inspired Robot
We have designed an adaptive analogue VLSI neuromorphic chip that will be used to interface MEM wind sensors to an insectinspired robot. The main chip components are a sensory inte...
Y. Zhang, A. Hamilton, R. Cheung, B. Webb, P. Argy...