Sciweavers

857 search results - page 34 / 172
» Implementing a STARI chip
Sort
View
PCI
2005
Springer
14 years 3 months ago
TSIC: Thermal Scheduling Simulator for Chip Multiprocessors
Abstract. Increased power density, hot-spots, and temperature gradients are severe limiting factors for today’s state-of-the-art microprocessors. However, the flexibility offer...
Kyriakos Stavrou, Pedro Trancoso
DATE
2003
IEEE
151views Hardware» more  DATE 2003»
14 years 3 months ago
SPIN: A Scalable, Packet Switched, On-Chip Micro-Network
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
Adrijean Andriahantenaina, Hervé Charlery, ...
ICRA
2000
IEEE
106views Robotics» more  ICRA 2000»
14 years 2 months ago
Toward Biomorphic Control Using Custom aVLSI CPG Chips
The locomotor controller for walking, running, swimming, and flying animals is based on a Central Pattern Generator (CPG). Models of CPGs as systems of coupled non-linear oscillato...
M. Anthony Lewis, Ralph Etienne-Cummings, Avis H. ...
DAC
1999
ACM
14 years 2 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
JCP
2008
119views more  JCP 2008»
13 years 9 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi