857 search results - page 35 / 172 » Implementing a STARI chip |
DAC
2008
ACM
14 years 10 months ago
2008
ACM
In this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to faulttolerant, Massively Parallel Multi-Processors Systems on Chip (MP...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
ISCAS
2008
IEEE
14 years 4 months ago
2008
IEEE
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...