857 search results - page 38 / 172 » Implementing a STARI chip |
SEUS
2009
IEEE
14 years 4 months ago
2009
IEEE
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
DFT
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper presents a new routing protocol of network-on-chip(Noc) called ‘Source Routing for Noc’(SRN) for fault tolerant communication of Systems-on-chip(Soc). The proposed ...
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
FPL
2007
Springer
14 years 3 months ago
2007
Springer
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...