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HPCA
2006
IEEE
14 years 9 months ago
The common case transactional behavior of multithreaded programs
Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed a...
JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen...
CASES
2008
ACM
13 years 11 months ago
Active control and digital rights management of integrated circuit IP cores
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
Yousra Alkabani, Farinaz Koushanfar
IEEEARES
2009
IEEE
14 years 3 months ago
Defeating Dynamic Data Kernel Rootkit Attacks via VMM-Based Guest-Transparent Monitoring
—Targeting the operating system kernel, the core of trust in a system, kernel rootkits are able to compromise the entire system, placing it under malicious control, while eluding...
Junghwan Rhee, Ryan Riley, Dongyan Xu, Xuxian Jian...
ISCAS
2007
IEEE
108views Hardware» more  ISCAS 2007»
14 years 3 months ago
Optimal Synthesis of MITE Translinear Loops
— A procedure for synthesizing multiple-input translinear element (MITE) networks that implement a given system of translinear–loop equations (STLE) is presented. The minimum n...
Shyam Subramanian, David V. Anderson, Paul E. Hasl...
ISCAS
2006
IEEE
147views Hardware» more  ISCAS 2006»
14 years 2 months ago
Triangular systolic array with reduced latency for QR-decomposition of complex matrices
- The novel CORDIC-based architecture of the these weights (combiner unit). The implementation of the Triangular Systolic Array for QRD of large size complex combiner unit is rathe...
Alexander Maltsev, V. Pestretsov, Roman Maslenniko...