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ARITH
2005
IEEE
14 years 2 months ago
Table Lookup Structures for Multiplicative Inverses Modulo 2k
We introduce an inheritance property and related table lookup structures applicable to simplified evaluation of the modular operations “multiplicative inverse”, “discrete l...
David W. Matula, Alex Fit-Florea, Mitchell Aaron T...
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Bitwidth-aware scheduling and binding in high-level synthesis
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, J...
SAMOS
2004
Springer
14 years 2 months ago
A Novel Data-Path for Accelerating DSP Kernels
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
Michalis D. Galanis, George Theodoridis, Spyros Tr...
ASPLOS
2010
ACM
14 years 3 months ago
Request behavior variations
A large number of user requests execute (often concurrently) within a server system. A single request may exhibit fluctuating hardware characteristics (such as instruction comple...
Kai Shen
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 10 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner