On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
On account of the enormous amounts of rules that can be produced by data mining algorithms, knowledge post-processing is a difficult stage in an association rule discovery process....
Julien Blanchard, Bruno Pinaud, Pascale Kuntz, Fab...
— Emulating Output Queued (OQ) Switch with sustainable implementation cost and low fixed delay is always preferable in designing high performance routers. The SwitchMemory-Switch...
Nan Hua, Yang Xu, Peng Wang, Depeng Jin, Lieguang ...