244 search results - page 32 / 49 » Implementing the scale vector-thread processor |
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
HPDC
2010
IEEE
13 years 8 months ago
2010
IEEE
In this paper we present a multi-GPU parallel volume rendering implemention built using the MapReduce programming model. We give implementation details of the library, including s...
CLUSTER
2008
IEEE
2008
IEEE
A trace-driven emulation framework to predict scalability of large clusters in presence of OS Jitter
14 years 2 months ago
—Various studies have pointed out the debilitating effects of OS Jitter on the performance of parallel applications on large clusters such as the ASCI Purple and the Mare Nostrum...
EMSOFT
2005
Springer
14 years 1 months ago
2005
Springer
Real-time systems have reached a level of complexity beyond the scaling capability of the low-level or restricted languages traditionally used for real-time programming. While Met...
ICS
2009
Tsinghua U.
14 years 4 days ago
2009
Tsinghua U.
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...