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EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
13 years 11 months ago
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
DSD
2006
IEEE
116views Hardware» more  DSD 2006»
14 years 1 months ago
Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*
In this paper we present an approach for the mapping optimization of fault-tolerant embedded systems for safetycritical applications. Processes and messages are statically schedul...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
GECCO
2007
Springer
148views Optimization» more  GECCO 2007»
13 years 11 months ago
How genetic algorithms can improve a pacemaker efficiency
Laurent Dumas, Linda El Alaoui
ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
13 years 12 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf