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ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 2 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 1 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
ASPDAC
2008
ACM
115views Hardware» more  ASPDAC 2008»
13 years 9 months ago
An optimal algorithm for sizing sequential circuits for industrial library based designs
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Che...
PERCOM
2003
ACM
14 years 7 months ago
Evaluation of Kalman Filtering for Network Time Keeping
Time information is critical for a variety of applications in distributed environments that facilitate pervasive computing and communication. This work describes and evaluates a no...
Aggelos Bletsas
SENSYS
2004
ACM
14 years 1 months ago
The flooding time synchronization protocol
Wireless sensor network applications, similarly to other distributed systems, often require a scalable time synchronization service enabling data consistency and coordination. Thi...
Miklós Maróti, Branislav Kusy, Gyula...