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MST
2002
169views more  MST 2002»
13 years 7 months ago
Bulk Synchronous Parallel Algorithms for the External Memory Model
Abstract. Blockwise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is f...
Frank K. H. A. Dehne, Wolfgang Dittrich, David A. ...
DAC
2006
ACM
14 years 1 months ago
Clock buffer and wire sizing using sequential programming
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 5 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
IPPS
2007
IEEE
14 years 1 months ago
Task-pushing: a Scalable Parallel GC Marking Algorithm without Synchronization Operations
This paper describes a scalable parallel marking technique for garbage collection that does not employ any synchronization operation. To achieve good scalability, two major design...
Ming Wu, Xiao-Feng Li
DCOSS
2008
Springer
13 years 9 months ago
Time Synchronization in Heterogeneous Sensor Networks
Heterogeneous sensor networks consisting of resource-constrained nodes as well as resource-intensive nodes equipped with high-bandwidth sensors offer significant advantages for dev...
Isaac Amundson, Branislav Kusy, Péter V&oum...