Clock buffer and wire sizing using sequential programming

This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequential programming-based buffer/wire sizing is used. Then, a new formulation of clock skew minimization that uses quadratic programming and considers sub-critical skews in addition to the most critical skews is presented. The quality of results are verified to be more robust using Monte Carlo simulations to account for process sensitivity. For the same power budget, the sequential quadratic programming (SQP) method has better expected skew, standard deviation, and overall CPU time on average. Categories and Subject Descriptors J.6 [Computer-Aided Engineering]: Computer-Aided Design General Terms Algorithms, Design. Keywords Clock tree synthesis, skew, robust design.

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
• Keywords: Clock Skew Minimization, Computer Architecture, DAC 2006, Quadratic Programming, Sequential Quadratic Programming