A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa...
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage -between 2 and 2.5 times the threshold voltage Vt of the transistors. A d...
The application of information retrieval techniques in interactive environments requires systems capable of efficiently processing vague queries. To reach reasonable response tim...
Testing of multi-threaded programs poses enormous challenges. To improve the coverage of testing, we present a framework named CONTESSA that augments conventional testing (concrete...
The explosive growth of new multimedia services over the Internet necessitates efficient network management. Improved network management systems are expected to simultaneously prov...