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DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 3 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
ISPD
2000
ACM
126views Hardware» more  ISPD 2000»
14 years 2 months ago
A practical clock tree synthesis for semi-synchronous circuits
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui,...
MOBICOM
1999
ACM
14 years 2 months ago
Next Century Challenges: RadioActive Networks
A key challenge facing wireless networking is to utilize the spectrum as e ciently as possible given current channel conditions and in the most e ective way for each application. ...
Vanu G. Bose, David Wetherall, John V. Guttag
HPCN
1994
Springer
14 years 2 months ago
Three-Dimensional Simulation of Semiconductor Devices
The exact knowledge of the heat flow in heterojunction bipolar transistors (HBT) during power operation is an important key factor for the systematic improvement of power density,...
Wilfried Klix, Ralf Dittmann, Roland Stenzel
AOSD
2007
ACM
14 years 2 months ago
C-CLR: a tool for navigating highly configurable system software
In order to accommodate the spectrum of configuration options currently required for competitive system infrastructures, many systems leverage heavy usage of C preprocessor contro...
Nieraj Singh, Celina Gibbs, Yvonne Coady