34 search results - page 3 / 7 » Improved Effective Capacitance Computations for Use in Logic... |
EUROPAR
1998
Springer
13 years 12 months ago
1998
Springer
This paper aims to improve locality of references by suitably choosing array layouts. We use a new definition of spatial reuse vectors that takes into account memory layout of arra...
IPPS
2000
IEEE
14 years 2 days ago
2000
IEEE
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
DAC
2004
ACM
13 years 11 months ago
2004
ACM
The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase nume...
HIPC
2000
Springer
13 years 11 months ago
2000
Springer
Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas suc...