Sciweavers

59 search results - page 7 / 12
» Improved indexing for cache miss reduction in embedded syste...
Sort
View
CODES
2000
IEEE
13 years 12 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
ICS
2005
Tsinghua U.
14 years 1 months ago
A heterogeneously segmented cache architecture for a packet forwarding engine
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
Kaushik Rajan, Ramaswamy Govindarajan
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 4 months ago
SPM management using Markov chain based data access prediction
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 25 days ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
CODES
2003
IEEE
14 years 25 days ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...