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» Improvement of ASIC Design Processes
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VLSID
2002
IEEE
172views VLSI» more  VLSID 2002»
14 years 11 months ago
Improvement of ASIC Design Processes
With device counts on modern-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this con...
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
DATE
2010
IEEE
263views Hardware» more  DATE 2010»
14 years 4 months ago
SCOC3: a space computer on a chip
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
Franck Koebel, Jean-François Coldefy
VLSID
2002
IEEE
106views VLSI» more  VLSID 2002»
14 years 11 months ago
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
Tony Han, Sri Parameswaran
DAC
2009
ACM
14 years 3 months ago
RegPlace: a high quality open-source placement framework for structured ASICs
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
14 years 3 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton