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» Improvement of ASIC Design Processes
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GLVLSI
2002
IEEE
127views VLSI» more  GLVLSI 2002»
14 years 12 days ago
A new look at hardware maze routing
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
John A. Nestor
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
14 years 1 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
Model-based synthesis and optimization of static multi-rate image processing algorithms
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
Joachim Keinert, Hritam Dutta, Frank Hannig, Chris...
ICIP
1995
IEEE
14 years 9 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C...
EVOW
2001
Springer
13 years 12 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...