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» Improvement of ASIC Design Processes
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ICCAD
1994
IEEE
122views Hardware» more  ICCAD 1994»
14 years 2 months ago
An enhanced flow model for constraint handling in hierarchical multi-view design environments
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
Pieter van der Wolf, K. Olav ten Bosch, Alfred van...
DAC
2004
ACM
14 years 11 months ago
Defect tolerant probabilistic design paradigm for nanotechnologies
Recent successes in the development and self-assembly of nanoelectronic devices suggest that the ability to manufacture dense nanofabrics is on the near horizon. However, the trem...
Margarida F. Jacome, Chen He, Gustavo de Veciana, ...
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 4 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
CAD
2000
Springer
13 years 10 months ago
Managing digital libraries for computer-aided design
This paper describes our initial efforts to deploy a digital library to support computer-aided collaborative design. At present, this experimental testbed, The Engineering Design ...
William C. Regli, Vincent A. Cicirello
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 3 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita