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» Improvement of ASIC Design Processes
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125
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ISCAS
2007
IEEE
138views Hardware» more  ISCAS 2007»
15 years 9 months ago
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
Henry H. Y. Chan, Zeljko Zilic
135
Voted
ICMCS
2006
IEEE
107views Multimedia» more  ICMCS 2006»
15 years 9 months ago
A Flexible Content-Based Approach to Adaptive Image Compression
Recent research in image compression has focused on lossy compression algorithms. However, the baseline implementations of such algorithms generally use a universal quantization p...
Alexander Wong, William Bishop
EUROMICRO
2000
IEEE
15 years 8 months ago
Behavior-Preserving Transformations for Design-for-Test
An important aspect in the design of hardware/software systems is design-for-test. Improving the testability of a hardware/software system typically implies improving the controll...
Jeroen Voeten, Harald P. E. Vranken
DAC
2006
ACM
16 years 4 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
127
Voted
CAINE
2007
15 years 5 months ago
A Novel Peak Detection Algorithm for Use in the Study of Machining Chip Segmentation
The study of how metal deforms and flows as parts are machined yields important insights into the metal cutting process. Improvements in high-speed digital imaging and image proce...
Eric Whitenton, Robert Ivester, Jarred Heigel