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» Improvement of ASIC Design Processes
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103
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BCSHCI
2009
15 years 4 months ago
Evolving and augmenting worth mapping for family archives
We describe the process of developing worth maps from field research and initial design sketches for a digital Family Archive, which resulted in a more simple and flexible worth m...
Gilbert Cockton, David S. Kirk, Abigail Sellen, Ri...
108
Voted
ICIP
2007
IEEE
16 years 5 months ago
DSP Implementation of Deblocking Filter for AVS
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...
Zhigang Yang, Wen Gao, Yan Liu, Debin Zhao
117
Voted
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 9 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
127
Voted
IFIP11
2004
114views Business» more  IFIP11 2004»
15 years 5 months ago
Update/Patch Management Systems: A Protocol Taxonomy with Security Implications
: Software fixes, patches and updates are issued periodically to extend the functional life cycle of software products. In order to facilitate the prompt notification, delivery, an...
Andrew M. Colarik, Clark D. Thomborson, Lech J. Ja...
DAC
2005
ACM
15 years 5 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...