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» Improvement of ASIC Design Processes
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IPPS
2007
IEEE
15 years 10 months ago
Stack Trace Analysis for Large Scale Debugging
We present the Stack Trace Analysis Tool (STAT) to aid in debugging extreme-scale applications. STAT can reduce problem exploration spaces from thousands of processes to a few by ...
Dorian C. Arnold, Dong H. Ahn, Bronis R. de Supins...
137
Voted
TCAD
2008
93views more  TCAD 2008»
15 years 3 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
135
Voted
EICS
2009
ACM
15 years 10 months ago
User evaluation of OIDE: a rapid prototyping platform for multimodal interaction
The Open Interface Development Environment (OIDE) was developed as part of the OpenInterface (OI) platform, an open source framework for the rapid development of multimodal intera...
Marilyn Rose McGee-Lennon, Andrew Ramsay, David K....
143
Voted
RTAS
2003
IEEE
15 years 9 months ago
Tool Set Implementation for Scenario-based Multithreading of UML-RT Models and Experimental Validation
This paper presents our tool set implementation for scenario-based multithreading of object-oriented realtime models and an accompanying experimental validation. Our tools enable ...
Jamison Masse, Saehwa Kim, Seongsoo Hong
153
Voted
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
15 years 9 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel