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» Improvement of ASIC Design Processes
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134
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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 8 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
AUTOMATICA
2005
134views more  AUTOMATICA 2005»
15 years 3 months ago
Robust output feedback regulation of minimum-phase nonlinear systems using conditional integrators
This paper is on the design of robust output feedback integral control for minimum-phase nonlinear systems with a well-defined relative degree. Previous work has shown how to desi...
Sridhar Seshagiri, Hassan K. Khalil
DAC
2008
ACM
16 years 4 months ago
The mixed signal optimum energy point: voltage and parallelism
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...
Brian P. Ginsburg, Anantha P. Chandrakasan
114
Voted
ICDCSW
2005
IEEE
15 years 9 months ago
Adding Context Information to Digital Photos
In a user centered design process, we investigate what context information may be used to augment digital photos with additional meta information. We describe our initial findings...
Paul Holleis, Matthias Kranz, Marion Gall, Albrech...
100
Voted
IWPC
2005
IEEE
15 years 9 months ago
What Can Programmer Questions Tell Us About Frameworks?
In order to make frameworks easier to use we need to better understand the difficulties that programmers have with them. The questions that programmers ask give clues to the qual...
Daqing Hou, Kenny Wong, H. James Hoover