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» Improvement of ASIC Design Processes
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CODES
2009
IEEE
14 years 2 months ago
On compile-time evaluation of process partitioning transformations for Kahn process networks
Kahn Process Networks is an appealing model of computation for programming and mapping applications onto multi-processor platforms. Autonomous processes communicate through unboun...
Sjoerd Meijer, Hristo Nikolov, Todor Stefanov
EIT
2008
IEEE
13 years 9 months ago
Experiments in attacking FPGA-based embedded systems using differential power analysis
Abstract--In the decade since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer securit...
Song Sun, Zijun Yan, Joseph Zambreno
DELTA
2008
IEEE
14 years 2 months ago
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications
The advances of CMOS technology towards 45 nm, the high costs of ASIC design, power limitations and fast changing application requirements have stimulated the usage of highly reco...
Hans G. Kerkhoff, Jarkko J. M. Huijts
DAC
1995
ACM
13 years 11 months ago
A Transformation-Based Approach for Storage Optimization
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
Wei-Kai Cheng, Youn-Long Lin
ITC
2003
IEEE
92views Hardware» more  ITC 2003»
14 years 25 days ago
Infrastructure IP for Back-End Yield Improvement
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a botto...
L. Forli, Jean Michel Portal, Didier Née, B...