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» Improvement of ASIC Design Processes
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ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
14 years 22 days ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
DEXAW
2007
IEEE
124views Database» more  DEXAW 2007»
13 years 9 months ago
A Process Improvement Approach to Improve Web Form Design and Usability
The research presented in this paper is an examination of how the concepts used in process improvement may be applied to a web form to improve design and usability. Although much ...
Sean Thompson, Torab Torabi
DAC
2004
ACM
14 years 8 months ago
Toward a methodology for manufacturability-driven design rule exploration
Resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase-shift mask (PSM) technology are deployed in modern processes to increase the fidelity ...
Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, De...
DAC
2007
ACM
14 years 8 months ago
Design Methodology for Pipelined Heterogeneous Multiprocessor System
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...
Seng Lin Shee, Sri Parameswaran
MVA
1992
173views Computer Vision» more  MVA 1992»
13 years 8 months ago
VLSI Optimal Edge Detection Chip: Canny-Deriche Filter
This paper presents the design of an ASIC intended for optimal edge detection of blurred and noisy 2-D images. The chip has a parallel and pipelined architecture which processes a...
Mohamed Akil, Nizar Zarka