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» Improvement of ASIC Design Processes
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VTS
2005
IEEE
90views Hardware» more  VTS 2005»
14 years 1 months ago
Soft Error Mitigation for SRAM-Based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
RSP
2003
IEEE
176views Control Systems» more  RSP 2003»
14 years 22 days ago
Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, A...
CASES
2006
ACM
13 years 11 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 2 months ago
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
—The IEEE 802.15.4a amendment has introduced ultra-wideband impulse radio (UWB IR) as a promising physical layer for energy-efficient, low data rate communications. A critical p...
Christian Bachmann, Andreas Genser, Jos Hulzink, M...
RTAS
2005
IEEE
14 years 1 months ago
VPN Gateways over Network Processors: Implementation and Evaluation
Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, ...
Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Yuan-C...