231 search results - page 4 / 47 » Improvements to combinational equivalence checking |
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, ...
RECOSOC
2007
13 years 8 months ago
2007
A method for inferring latches from combinational loops in a netlist using boolean equations is proposed in this paper. The method takes advantage of the solutions structure of th...
ENTCS
2007
13 years 7 months ago
2007
We describe techniques for diagnosing errors in formal equivalence checking of RTL and transistor level models of high performance microprocessors at Freescale Semiconductor Inc. ...
ET
2010
13 years 5 months ago
2010
—Designers often apply manual or semi-automatic loop and data transformations on array and loop intensive programs to improve performance. For the class of static affine program...
GLVLSI
2005
IEEE
14 years 21 days ago
2005
IEEE
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...