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CODES
2005
IEEE
14 years 1 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
IEEEPACT
2008
IEEE
14 years 2 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
CVPR
2009
IEEE
15 years 2 months ago
Cooperative Mapping of Multiple PTZ Cameras in Automated Surveillance Systems
Due to the capacity of pan-tilt-zoom (PTZ) cameras to simultaneously cover a panoramic area and maintain high resolution imagery, researches in automated surveillance systems wi...
Andreas Koschan, Anis Drira, Chung-Chen Chen, Mong...
TSP
2010
13 years 2 months ago
Optimization and analysis of distributed averaging with short node memory
Distributed averaging describes a class of network algorithms for the decentralized computation of aggregate statistics. Initially, each node has a scalar data value, and the goal...
Boris N. Oreshkin, Mark Coates, Michael G. Rabbat
PARELEC
2006
IEEE
14 years 1 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich